Processes: we used external fabs to make our ICs; the idea was to have design rules compatible with at least two MOS processes in the UK, but in practice most of the designs were run on a Plessey process which ran at Swindon and later at Roborough. This was a metal gate process, using 2" wafers in the late 1970s! Gate length was, I think, 0.7 mil or 17 um in today's language.
Metal gate means the process is not self-aligned (cf. today's silicon gate), and this requires a fairly large overlap between the gate and the source/drain diffusions resulting in a significant gate to source/drain capacitance. In turn this means that clock signals on the MOS gates of the dynamic logic structures degrade the output logic level further, requiring additional bulk-up capacitance.
Further designs: after my first IC worked, much to my surprise, I was sent to help out another engineer working on a dialler chip. This had programmable parameters, and could use either pulse or multitone signalling. The logic was quite complex and we soon found ourselves in the situation where fixing a problem in one area would cause a problem in another area. After a while I had the idea of using a flowchart to design some kind of high-level structure, then implementing that in logic gates. This worked beautifully; nowadays we would most likely use a state rather than a flow diagram. When we got the silicon back there was one fault - one of the outputs pulsed for far too short a time. Our first assumption was that this was a fault in the output stage (oh how easy it is to jump to conclusions) until the boss suggested we look closely at the simulation output. Sure enough, the fault was there in the simulation; we had failed to see it - it showed the output going high for just one clock cycle.
We also used non-volatile memory. After a brief foray with General Instrument's MNOS (Metal nitride oxide semiconductor) EAROM (electrically alterable ROM) we switched to Intel's EEPROM. This required a fair bit of logic to interface it to a micro, including some rather long time-outs.
|A hard day at the office|
These functions were quite easy to incorporate into a "glue-logic" chip, my next project. This was chosen as a test vehicle for ALICE, a piece of software which had been developed by TMC to do automatic layouts from a netlist. This produced results that were rather larger than the conventional layouts, but the time and cost saving was considered worth it for this chip which was rather low volume. Funnily enough, the engineer in charge of running the program found an error while the masks were being made. I was able to resimulate and luckily it turned out that this error did not affect the function; this in turn meant my logic had redundancy - quite unintentional but fortunate! So we kept it all quiet and everyone was happy. Should have run that fault coverage program I suppose!
Our PABX was very successful. The next generation product was to have ever more features, so in turn the controlling computer had to be more powerful (i.e. something faster than 1 MHz). I had the opportunity to do a lot of the processor design; we stayed with Intel but moved up to the 8088. We took the opportunity to integrate more of the computer's hardware, but this required at least some fast logic. We decided to use a standard cell offering from Plessey called Microcell; this was a pure NMOS technology with depletion loads. The flip flops were fixed height cells but one could place gate input transistors and load transistors anywhere on a grid, including in the routing channel (the layout was done on graph paper, and was later digitised). This allowed enormous flexibility - one could have gates distributed over a large area. However we had only one metal layer so you got quite skilled at clever placement and wiring.
(Old and dirty) Microcell chip - photo courtesy PP photography
Another technique we tried with a lot of success was to design multi-channel chips, where the logic for generating the next state and outputs from the present state and inputs was shared between channels. This required a more formal design method, no bad thing! We had the use of a logic minimization program from Edinburgh University which was interesting - a small variation in the state equations could result in big differences in run time. Actually this showed up one of those irritating things that happen when a program is designed by someone with little IC experience - the success criterion was measured by the number of terms in the equations; what mattered to us was transistor area.
Around this time our first CMOS chip got designed. The gate density was very poor compared with NMOS + depletion loads, simply because twice as many transistors were need for the logic chain (and also the well spacing was quite big). The big CMOS advantage of low power didn't matter too much in most of our applications.
I did one more IC at TMC - a general-purpose tone generator - before moving on to manage a new PABX design; ISDN was dawning and digital was the way to go, especially as data switching in the office was being thought about. Eventually though an invitation came to join a major multinational semiconductor company. My humble Renault with doors held closed by string was no competition for a company Audi and fat salary cheque.